1. Field of the Invention
The present invention pertains, in general, to a semiconductor element and a method of fabricating the same and, more particularly, to a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and a method of fabricating the same, using a selective epitaxial growth (SEG) process.
2. Description of the Related Art
As well-known to those skilled in the art, Field Effect Transistors (FET) have been gradually scaled down in size in accordance with the recent trend toward small-sized, lightweight, and slim electronic devices. However, as a result of the downsizing of the FETs, the corresponding effective channel lengths are reduced. This, in turn, causes an undesirable effect, referred to as the “short-channel” effect, which degrades the punch-through characteristics between a source electrode and a drain electrode of the FET. In an attempt to avoid this problem, a shallow junction source/drain structure has been developed. According to this configuration, a source and a drain are constructed in the form of an LDD (Lightly Doped Drain) structure to suppress the short channel effect. However, such an LDD structure is limited in use, since it can be applied to only a semiconductor element with a gate line width of 0.35 μm or larger to suppress the short channel effect, and cannot be applied to a semiconductor element with a gate line width of 0.35 μm or less. This is because there is a limit to the extent to which the depth of the junction can be reduced, and thus formation of a junction in the LDD structure is impractical or impossible.